Magnetic control device



July 21, 1970 c F. STRAWN I I 3,52

MAGNETIC CONTROL DEVICE Filed Dec. 28, 1966 2 Sheets-Sheet l r- 7 I l 4L i 7 4 [M2, 1 ii}; 7 9 c j POWER AMPLITUDE INVENTOR CHARLES E 5TRAw/vAfforn eys y 21, 1970 c. F. STRAWN 7 3,521,253

MAGNETIC CONTROL DEVICE Filed Dec. 28, 1966 2 sheets sheet 2 A C 9 POWER"9 [Z 2; FL 0 n W /l7 6 1% d -INVENTOR CHARLEJ' E Sm/1w Aflarggys UnitedStates Patent ()1 3,521,253 Patented July 21, 1970 3,521,253 MAGNETIC COTROL DEVICE Charles F. Strawn, Arlington, Tex., assignor to JohnsonService Company, Milwaukee, Wis., a corporation of Wisconsin Filed Dec.28, 1966, Ser. No. 605,445 Int. Cl. H03k 17/64; G11c 11/08 US. Cl.340-174 7 Claims ABSTRACT OF THE DISCLOSURE The present disclosureincludes a square loop core having a pair of apertures defining threelegs and including a main memory magnetic path including all three legsand a secondary gating path including only two legs. A 1

This invention relates to a magnetic control device wherein anelectrical signal represents a quantity of value to be remembered.

In control systems and other electrical control and telemetryapplications, an output may be desirably controlled in connection withpreselected information fed into the system in the form of an electricalpulse signal. In many such applications, it is highly desirable that theinformation be retained for relatively long periods of time, and furtherthat they maintain the set level accurately. Such devices should also bereadily changed from one level to another and automatically resume thesame output level in the event of a restoration of power after a powerfailure.

A magnetic control or memory unit known as a transfluxor has beensuggested in the computer art for providing memory by storage orconditioning of a multiple apertured magnetic core having a set windingand a saturable reactor or transformer output means. In the transfluxor,a magnetic core material is employed having a substantially rectangularhysteresis loop and having a main aperture and a coupling aperture whichdefines three legs. The first magnetic path includes all three legs anda second magnetic path surrounding the second aperture includes only thetwo legs. The two legs of the latter path are selected and arranged suchthat they will become magnetically saturated prior to saturation of themain circuit including all three legs. A control signal is applied tothe main path to establish a preselected saturation level after whichthe signal on the applied winding in the second aperture or controlaperture provides for a selective transfer of flux between thetwo smalllegs such that the output is controlled in accordance with thesaturation of the main path without affecting that saturation level.Thus, the device in essence provides a memory in accordance with theinput signal.

The present invention is particularly directed to the use of such a corestructure connected in a novel manner to provide high level powercircuits and controls, Generally, in accordance with the presentinvention, the core structure is formed with at least a pair ofapertures defining at least three legs and including a main memorymagnetic path including all three legs and a secondary gating pathincluding only two legs. A control winding is coupled to the main pathand a separate gate winding is coupled to each of the gate legs. Thegate windings are connected to an AC. power supply through suitablerectifying means to establish a saturating magnetic amplifying device.The gate windings carry the alternate half cycles of each full cycle ofthe alternating current input power and are so wound that they establishoppositely directed fluxes about the two gate legs and the bridgingportion of the core.

In operation, the half cycle current flowing through the associated gatewinding is determined by the selfinductance of that gate winding. Ifthere is no presaturation or set point saturation, the flux will flowthrough the minor path of the core structure increasingand decreasing inthe respective legs. The minor path never however reaches saturation andconsequently the self-inductance of the winding is high and only a veryminimal current, corresponding to a small exciting or magnetizingcurrent, flows to the load. This provides a minimum output correspondingto a zero fiux level in the remainder of the core. If a voltage isapplied to the control winding, it establishes a flux level in the corestructure including the gate legs and generally, in the same directionas that established by current flow in the corresponding gate winding.Consequently, when power is applied to the gate windings, the fiuxthereof adds to that established by the control winding. The gate legassociated with the conducting gate Winding saturates some time prior tothe end of the corresponding half cycle depending on the level of theset point saturation and the self-inductance of the winding switchesrapidly to a minimal level. Thereafter, a large current flows in thegate winding and the load.

When the control or preset saturation level is increased or decreased inamplitude, the saturation point is reached in an earlier or later partof the half cycle and similarly increases or decreases the power currentlevel. A feedback circuit is interconnected between the load circuit andthe set source for the control winding. The control winding is energizedin accordance with the difference in the input signal and the voltage inthe output voltage signal. The negative feedback establishes a precisecontrol or set point and permits raising and lowering of the set pointwithout reversal of the phase or polarity of the set source.

The control unit of the present invention can be readily interconnectedto control an alternating or direct current load. Further, an isolationtransformer may be inserted to couple the load to the memory circuit. Asthe memory unit provides a rapid or step change in the load or output,it is readily adapted to the controlling of triggered devices such asilicon controlled rectifiers, Triacs and the like.

The present invention thus provides a simple, reliable and relativelyinexpensive analog signal control with a very rapid response and anessentially indestructible memory. The invention provides a memorydevice wherein the gate winding may be connected directly in the loadcircuit and is therefore particularly adapted to a servo type control.

The drawings furnished herewith illustrate preferred constructions ofthe present invention in which the above advantages and features areclearly disclosed as well as others which will be clear from thefollowing description.

In the drawings:

FIG. 1 is a schematic circuit diagram employing an analog memory unitconstructed in accordance with the present invention; 7

FIG. 2 is a graphical view showing the output voltage and current withvarying set points;

FIG. 3 is a pictorial view of the memory unit constructed in accordancewith the present invention; 7

FIG. 4 is an exploded view of a pair of laminations employed in theconstruction of the magnetic core shown in FIG. 3;

FIG. is a schematic circuit diagram similar to FIG. 1 showing the unitinterconnected to provide a direct current output;

FIG. 6 is a similar schematic circuit diagram with the device connectedto provide an isolated alternating current output;

FIG. 7 is a schematic circuit diagram showing the memory unitinterconnected in a control circuit for a bi-directional triggered solidstate switch such as a Triac; and

FIG. 8 is a view similar to FIG. 7 showing the device applied to controlthe firing of a pair of silicon controlled rectifiers.

Referring to the drawings and particularly to FIG. 1, the analog memoryunit of the present invention is shown including a generally rectangularmagnetic core 1 having a pair of apertures defining a control windingleg 2 and a pair of similar load or gate winding legs 3 and 4. In theillustrated embodiment of the invention, the control winding leg 2 isshown to the left side of the core structure and the gate legs 3 and 4are shown to the right side. The gate legs 3 and 4 are similarlyconstructed and are of a substantially smaller cross section than thatof the control winding leg. The two legs 3- and 4 as shown are eachone-half the width of the leg 2 and provide a corresponding magneticpath. A control winding 5 is wound on the control winding leg 2 andconnected to a suitable direct current signal source. A pair of gatewindings 7 and 8 is wound one each on the respective legs 3 and 4.Windings 7 and 8 are connected in parallel circuit to A.C. power supplylines 9 in series with a load 10, shown as a resistor. The paralleledpaths defined by windings 7 and 8 each includes a diode 11 and 12,respectively, polarized in opposite directions with respect to the load10. The A.C. power supply lines 9 may be connected to any suitablesource such as the conventional 60 cycle alternating current, 110 voltpower distribution system of this country. The windings 7 and 8 in theillustrated embodiment of the invention are wound to establishoppositely directed fluxes with respect to a path including the two legs3 and 4 and the immediately adjacent bridging portion, as shown by thesolid line 13 for winding 7 and by the dotted line 14 for the winding 8.

The magnetic path including the legs 3 and 4 in combination with thepolarized connection of the gate Windings 7 and 8 by the rectifiers 11and 12 to the A.C. power supply defines a saturating magnetic amplifiermeans having the high gain characteristic of a self-saturating magneticamplifier, the output of which is responsive to a premagnetization levelof the core 1 as a result of energization of the control winding 2.

The magnetic core 1 is formed of a material having an essentiallyrectangular magnetic hysteresis loop;- for example, nickel-iron, ferriteor similar material. As is known, if a direct current flows throughwinding 5, the core 1 is magnetized to a related level and maintainssuch level independently of the continuance of the DC. signal. The setmagnetic state, with proper core material, will in fact remainessentially static for an unlimited period of time. Further, because ofthe rectangular characteristic, the impedance of a winding associatedwith such a core may be made to change rapidly at the corners of thecharacteristic.

In the operation of the analog memory unit, the alternate half cycles ofthe A.C. power supply are impressed upon the load 10 in series with therespective windings 7 and 8. Thus, during the half cycle when the toppower supply line 9 in the drawing is positive, the diode 11 is biasedin a forward direction and current flows through the diode 11, theassociated winding 7 and the load 10. During the alternate half cycle,the power supply reverse biases the diode 11 and forward biases diode 12whereupon A.C. power flows through the resistor or load 10 in theopposite direction in series with the alternate gate winding 8 and thediode 12. The level of current or power to the load is directlycontrolled by setting the level of magnetization of the core 1 bymomentary energization of the winding 5.

The operation of the memory unit is described in connection with thegraphical illustration of FIG. 2 wherein three succeeding full cycles ofthe alternating current power supply are shown by the dotted line curve15 and the output current shown for three different levels ofmagnetization of core 1 by the full line curve 16. The first full cycleis shown with the core at essentially a zero magnetization level; thatis, the control winding 5 has not been energized and the core 1 is in aneutral state. During the first half cycle during which voltage isapplied to load 10 in series with the rectifier 11, and winding 7, theflux flows in the counterclockwise direction as shown by line 13. TheA.C. power supply is selected with a maximum amplitude which isinsufiicient to estab lish saturation of the path including the two legs3 and 4 and the adjacent bridging portion. As the core is at a zero fluxlevel and the applied voltage is such that the core legs 3 and 4 neverreach the saturation level, the impedance of the winding 7 is high andconsequently only a minimal current flow is established. This is shownby the corresponding portion of line 16. During the alternate halfcycle, the current flows in the Opposite winding 8 which is wound toestablish a clockwise or oppositely directed flux as shown by the dottedflux line. As it is in the direction opposite to the magnetizationestablished during the previous cycle, the impedance of the Winding 8remains high and only a similar minimal magnetizing current flowsthrough the load 10.

It was noted previously that the flux paths for the magnetic amplifyingportion of core 1 are essentially restricted to that of the coreimmediately adjacent to the gate legs 3 and 4. This is true because thealternate path through the control winding 2 provides a substantiallylonger path and consequently of a substantially greater reluctance. As aresult of this condition, the flux in the two legs 3 and 4 alternatelyincrease and decrease Without ever reaching saturation and the impedanceof the gate windings 7 and 8 remains high. Only the very smallexcitation or magnetizing current flows through the load 10. Thiscorresponds to a minimum output and a Zero flux level in the remainderof the core.

Although illustrated with the gate arms or legs of a smaller crosssection, a similar result may be obtained by forming the gate legs of amaterial which saturates at a lower flux density than the balance of thecore.

A DC. control signal is now momentarily applied to the control winding 5of a polarity establishing a flux downwardly through the legs 3 and 4such as to be additive in each leg with the flux established by theassociated winding. The level selected is such as to saturate the core 1including legs 3 and 4. The load current immediately rises to a maximumas shown in connection with the second full cycle of the applied voltagewave line 15. The flux produced by the gate windings 7 and 8 is in thesame direction as that established by the control winding 5. Whenwinding 7 is energized, the gate leg 3 is in a magnetically saturatedcondition and consequently the impedance is low such that the currentfollows the impressed signal. Since gate leg 3 is saturated no change influx level is produced in either gate leg by the current through winding7. During the next half cycle when winding 8 conducts, the impedance ofthe winding 8 remains at a correspondingly minimum level and the currentfollows the applied voltage. During the illustrated second completealternating current half cycle in FIG. 2, a maximum output current isestablished to load 10. This condition is maintained indefinitely evenafter the D.C. signal is removed from the winding as a result of thegenerally rectangular hysteresis characteristic of the core 1.

Now, if the core 1 is saturated to some intermediate flux level bysuitable momentary energization of the control winding 5, thecorresponding gate legs 3 and 4 are below saturation during the initialportion of the applied voltage. As a result, the corresponding windings7 and 8 present a high impedance during the initial portion of theapplied wave and the current is at a minimum or exciting current level.Referring to FIG. 2, at a point determined by the premagnetization leveland the applied voltage of the first half of the cycle, thecorresponding leg 3 rapidly switches from the unsaturated to thesaturated state as a result of the rectangular hysteretic characteristicof the material of the core 1 at which time the impedance of thecorresponding winding 7 rapidly decreases to a minimal value and thecurrent correspondingly increases essentially as a step function. Duringthe balance of the first half of the cycle, the current wave 16 followsthe input voltage wave 15. When the cycle reverses, the second winding 8conducts. The leg 4 is in an unsaturated state and consequently thewinding 8 presents a high impedance. At a point essentiallycorresponding to that in the first half of the cycle, the additive fluxof the preset magnetization and that of winding 8 establishes asaturated condition in the leg 4, whereupon the impedance rapidly dropsand the current wave 16 again increases to follow the applied voltageWave 15. Thus, a pulsating current is supplied to the load 10 with theconducting period being directly controlled by and proportional to thepremagnetization level established by the control winding 5. The averagepower supplied to the load 10 is maintained at the selected level.

The average power is varied by changing the premagnetization levelthrough appropriate energization of control winding 5 between theminimal exciting current level to a maximum level. As the load voltageand current may be of a much higher value than that required to controlthem, there is considerable amount of power gain in the device.

Although the core structure may be formed in any desired manner, ahighly satisfactory core structure is shown in FIGS. 3 and 4. Asdisclosed therein, the core 1 is formed of a plurality of E-shapedlaminations 17 which are stacked with the base portion of the alternateindividual laminations to the opposite sides of the rectangular core andwith the arms in superimposed relation. Each of the core laminations 17includes a control leg and a base portion of a similar Width and the twogate legs generally of one-half the Wdith of the control leg. Thelaminations are preferably formed of a nickel steel such as that soldunder the trademark Orthonol by Magnetics, Inc. (Butler, Pa.) or othersuitable material which has been annealed to provide maximum squarenessof the hysteresis loop. Each lamination 17 is provided with bolt orclamping holes 18 in the respective four corners and all edges arepreferably formed completely burr free and the laminations are extremelyflat. The edges should not be rolled or deformed for an optimum coreunit. The winding 5, 7 and 8 may be wound on suitable bobbins 19 and thecore laminations 17 interleaved therewith to form the core unit, asshown pictorially in FIG. 3. After assembly of the core laminations,they are interconnected by suitable nut and bolt units 20.

Referring particularly to FIG. 5, the analog memory device of thepresent invention is shown connected in a circuit to provide a directcurrent energization of a load 10 from AC. power supply lines 9.

In the illustrated embodiment of FIG. 5, a filtering capacitor 21 isconnected in parallel with the load resistor 10 and in series with theanalog memory device to the AC. power supply lines 9. The connection tothe AC. power supply lines includes a transformer 22 having a primaryconnected in the power supply lines 9. A center tapped secondary winding23 is provided having a center tap 24 connected as a common return leadto the one side of the paralleled resistor 10 and capacitor 21. Theopposite ends of the center tapped secondary winding 23 are connected tothe anodes of the respective diodes 11 and 12 forming a part of thesaturating magnetic amplifying portion of the analog memory unit. InFIG. 5, the diodes 11 and 12 are polarized in the same direction withrespect to the load 10 as a result of the use of the center tappedsecondary winding 23. During the first half cycle, assuming the polarityshown by the conventional dot, the diode 11 conducts and current flowsfrom the secondary winding 23 through the diode 11 and associated gatewinding 7, the load 10 and returns to the center tap 24 of thetransformer winding 23. The circuit path of the opposite gate winding 8is reverse biased by the polarity of the opposite half of the secondarywinding'23 connected between the diode 12 and the center tap 24. Duringthe next half cycle, the polarity reverses to forward bias the seconddiode 12 and reverse bias the previously conducting diode 11. Power isthen supplied to the load 10 from winding 23 between tap 24 and diode 12in series with the second gate winding 8. The windings 7 and 8 conductthe alternate half cycles as in the previous embodiment. The gatewindings 7 and 8 are again wound on legs 3 and 4 to establish a fluxpath as a result of current fiow through the windings as in FIG. 1.

The control winding 5 is connected to the signal voltage to beremembered shown for purposes of illustration and simplicity ofexplanation in this and the following figures by a battery 25 connectedacross a potentiometer 26. A tap 27 on the potentiometer 26 is connectedin series with a momentary set switch 28 to one side of an inputresistor 29 and a D.C. amplifier 30. The opposite side of the resistor29 and the amplifier 30 are connected by leads 31 and 32 in series withthe paralleled load resistor 10 and filter capacitor 21 to the common orreturn side of the battery 25 and potentiometer 26.

The output of D.C. amplifier 30 is connected directly across the controlwinding 5.

In the operation of the circuit of FIG. 5, the current flow through theload 10 is a direct current as a result of the center tapped secondarywinding 23 and the diodes 11 and 12. Current alternately flows throughthe gate windings 7 and 8 which are wound in the same direction inseries with the load resistor 10. The capacitor 21 provides a filteringaction to smooth or average the pulses of D.C. current and consequentlyestablish a relatively pure D.C. current flow in the load 10. The changein the impedance level of the effective winding 7 or 8 and the beginningof the point in each half cycle of appreciable conduction isresponsiveto the preset magnetization of the core 1 in the same manneras described with respect to :FIG. 1.

The signal source provides a variable D.C. voltage connected in serieswith the load voltage and of an opposite polarity across the inputresistor 29 in series with the switch 28.

When the switch 28 is closed, the voltage across the input resistor 29and therefore the signal to the amplifier 30 is determined by therelative level of the signal voltage and the average voltage appearingacross the load 10.

If the input control voltage at the signal source is higher than theload voltage, the D.C. amplifier 30 establishes a signal on controlwinding 5 to increase the output voltage level. This increases thepremagnetization level of core 1 including legs 3 and 4 in the directionof the flux of the active gate winding 7 or 8. As a result, theimpedance of windings 7 and 8 drops at an earlier point in each halfcycle and increases the output voltage in a manner similar to thatpreviously discussed.

It the output or load voltage is higher than the control signal voltage,a reverse signal occurs at the input to amplifier 30 and a reversecurrent is established through the control winding 5. This reduces thepremagnetization of the core and increases the gate winding magneticflux required to cause saturation of the path including the legs 3 and4. The impedance of the effective windings 7 and 8 remains high for alonger period and establishes a reduced output or load voltage. Theoutput voltage will thus always approach the control voltage and drivethe control current to a zero setting level.

The maximum error in output level set point is controlled by the voltagerequired in the control Winding or applied to the control winding toestablish a change in the flux level in the large portion of the core.

Although the DC. amplifier is not required or essential in the broadestaspects of this invention, it increases the voltage gain within thefeedback loop and therefore will improve the accuracy. Further, the DC.amplifier may provide an impedance match between a high impedancecontrol voltage source and the low impedance of the control winding 5.As a result, it can improve the speed of response.

Thus, the analog memory device of the present invention permits highlyaccurate control of a direct current output with a highly desirablememory feature. The saturating magnetic amplifier portion provides thecontrol with the reset magnetomotive force supplied from the controlcoil 5. The negative feedback illustrated in FIG. provides a highlysatisfactory means for establishing a very precise control point. Thecontrol point will be maintained over long periods of time and willremain set in the event of power failure and its reestablishment.

The analog memory device can also be employed with a suitable negativefeedback to energize an alternating current load; for example, as shownin FIG. 6'.

In the embodiment of FIG. 6, the analog memory device is constructed asshown in FIG. 1 with the A.C. power supply line 9 connected in serieswith an isolating transformer 33 to the output of the analog memorydevice. The transformer 33 includes a primary winding 34 connected inseries with the A.C. power supply lines 9 and the paralleled gatewindings 7 and 8, with the associated diodes 11 and 12 connected in theparalleled circuits as in FIG. 1. A first or load secondary winding 35of the transformer 33 is connected across and supplies power to a loadresistor A second or feedback secondary Winding 36 is center tapped asat 37 and connected in a full wave rectifying circuit including a pairof diodes 38 and 39 having their anodes connected to form a commonterminal. The cathodes of the diodes 38 and 39 are connected to theopposite ends of the secondary winding 36 and similarly polarized withrespect to the opposite ends to provide a full wave DC. output betweenthe center tap 37 and the common terminal ends of the diodes 38 and 39.An integrating resistor 40 and capacitor 41 are connected across the tap37 and the diodes to provide a DC. feedback signal. A suitable bleed-offresistor 42 is connected in parallel with the capacitor 41 to controlthe time constant of the feedback circuit. A variable control voltagesignal is represented by a battery 43 and potentiometer 44 connected incircuit with the feedback signal and a momentary control switch 45directly to winding 5.

In the circuit of FIG. 6, alternate half cycles of the powercurrent-flow alternately through the gate windings 7 and 8 in the samemanner as in FIG. 1 with the level of the current controlled directly bythe preset magnetization of the main path of the core 1. In this case,the feedback signal however is not taken directly from the load 10 butrather is taken from the center tapped winding 36, rectified, integratedand filtered to provide an average DC. voltage proportional to theaverage alternating current voltage applied to the load 10.

In the illustrated embodiments of the invention of FIGS. l6, the analogmemory device is shown connected in series with the load and thuscarries full load current and voltage. The invention provides a simpleand reliable analog memory device permitting operation directly at theavailable power line frequency and power level.

Further, as the device operates directly at the line frequency, itproduces an output wave signal which is particularly adapted for phasecontrolling of silicon controlled rectifiers, Triacs and similardevices.

A circuit showing the analog memory unit applied to phase control of aTriac 46 is shown in FIG. 7. As is well known, the Triac is a solidstate bilateral switch which is normally in an open or blocking state.The Triac includes a trigger or gate element 47 to receive a signal forfiring of the device into conductive state. A signal of either polarityapplied to the gate of the Triac while voltage is applied to the mainelements will trigger the device and it will conduct for the balance ofthe corresponding half cycle.

In FIG. 7, the load resistor 10 is connected in series with the Triac 46directly across the A.C. power supply lines 9. In the illustratedembodiment of the invention, the gate 47 is connected in series with acurrent limiting resistor 48 and a gate control resistor 49 across thegate input circuit of the Triac.

The analog memory unit is constructed as shown in FIG. 1 and connectedin series with resistor 49 across the A.C. power supply lines 9. In theillustrated embodiment of the invention, a separate feedback transformer50 has a primary winding 51 connected directly across the load 10 and acenter tapped secondary 52 connected in a feedback network 53corresponding to that shown in FIG. 6. The network 53 provides anaverage direct current signal which is algebraically added to the inputfrom a variable signal source represented by batterypotentiometernetwork 54 whenever a momentary switch 55 is closed, as in FIG. 6.

In the operation of the embodiment of the invention shown in FIG. 7, theTriac 46 normally opens the power circuit to the load 10 and also to theparalleled feedback transformer 50. In the absence of anypremagnetization set point of the control core 1, the small excitingcurrent flows through the gate windings 7 and 8 and the series gatecontrol resistor 49. The drop across the resistor 49 is insufficient todevelop a triggering voltage.

However, by premagnetization of the analog memory unit core 1, theimpedance of the windings 7 and 8 can be reduced at any selected pointin the half cycle such that the load current rises and develops a firingvoltage across the resistor 49, thereby firing or triggering the Triac46. Once triggered, the Triac conducts over the balance of the halfcycle.

The control unit operates at the power line frequency and thus providesa properly phased control signal for triggering the Triac in a mannerwhich permits varying the control signal over the full 180 degrees ofeach half cycle.

Triacs and similar bilateral switches at the present state ofdevelopment are relatively low power devices and consequently if higherpower levels must be controlled silicon controlled rectifiers may beemployed; for example, as shown in FIG. 8.

In FIG. 8, a pair of silicon controlled rectifiers 56 and 57 isconnected in parallel with each other and in series with the loadresistor 58 across the A.C. power supply lines 9. The rectifiers 56 and57 are oppositely polarized to conduct the alternate half cycles of theA.C. power supply and to thereby supply alternating current power to theload resistor 58. The silicon controlled rectifiers 56 and 57 areconnected to be controlled from the analog memory device through atransformer 59 having a primary winding 60 connected in series with theanalog memory unit and particularly the paralleled windings 7 and 8directly across the A.C. power supply lines 9 and thus in parallel withthe circuit of load 10 and rectifiers 56 and 57 as described above. Thetransformer 59 includes a pair of secondaries 61 and 62 connectedrespectively across the gate to cathode circuit of the silicon 9controlled rectifiers 56 and 57. A feedback network 63 supplies afeedback voltage proportional to the voltage across the load resistor 58to the input circuit 64, in the same manner as shown in FIG. 7.

In operation of the device, in the absence of paramagnetization of thecore 1 of the analog memory unit, the output is minimal and consequentlythe current through the primary 60 of transformer 59 is insufficient totrigger the silicon controlled rectifiers 56 and 57. It a set pointmagnetization of the analog memory core 1 is established, the impedanceof the windings 7 and 8 drops at a related point in the half cycle andthe current through the transformer winding 60 rises to a level totrigger the proper silicon controlled rectifier 56 or 57 during eachhalf cycle.

The circuit of FIG. 8 operates essentially in the same manner as thatdescribed with respect to FIG. 7 with the exception that the couplingtransformer 59 provides alternately eltective signals to the two siliconcontrolled rectifiers 56 and 57 to alternately trigger them in theappropriate half cycles.

The present invention has been described in a plurality of differenthighly useful circuits but its application may be extended to anyapplication wherein the output energization of a load is to beestablished in accordance with a low level power signal and which isdesired to retain over long periods of time. It can be advantageouslyapplied in servo systems for operation of hydraulic or pneumaticcontrols such as employed in temperature control systems. It can providecontrol of any load adapted to be phase controlled; for example,heating, lighting, motor drive speeds for fans, pumps, machine tools andthe like.

The control device can also be viewed as a latching relay means whichcan be locally or remotely controlled and connected to providepreselected load operation.

The present invention thus provides a highly improved analog memorydevice based on the concept of a saturating magnetic amplifier formingan integral part of the analog control core in such a manner that thedevice operates at power line frequency and voltage level. An analogmemory device of the present invention employing feedback does notrequire any change in the polarity of the input control signal to changethe output level of the system. Thus, the output is directly related tothe increase and decrease in the control signal. The gain associatedwith the device also permits establishment of precision control of theoutput from the input.

The present invention thus provides a very simple and inexpensive analogmemory device having Wide application in control circuitry andparticularly enclosed loop systems as a result of the high gain of thesystem permitting a feedback system.

Various modes of carrying out the invention are contemplated as beingwithin the scope of the following claims particularly pointing out anddistinctly claiming the subject matter which is regarded as theinvention.

I claim:

1. A magnetic control unit, comprising a multiple apertured magneticcore defining a magnetic control path, said core is a generallyrectangular laminated member including a plurality of generally E-shapedlaminations stacked with superimposed arms and with the base portion ofadjacent laminations to opposite sides of the core, the middle arm andone end arm defining a pair of gate legs and the second end arm defininga control leg, the gate legs and the immediately adjacent bridgingportion of the control path defining a magnetic saturating path, saidcore having an essentially square hysteresis loop characteristic andsaid gate legs being adapted to be saturated while said control legs andthe remainder of said control path is essentially below saturation,

at least one pair of gate windings provided, one winding on each of saidgate legs,

a load circuit means connecting said gate windings in circuit toalternating current input means having a varying current amplitudewithin each half cycle of the current input, an output connection meansand including selection means connecting said gate windings to conductthe alternate half cycle of the alternating current input, said gatewindings being con structed and connected to establish oppositelydirected flux loop including said gate leg and the immediately adjacentportion of the core bridging and two gate legs to define a saturatingmagnetic amplifier means,

at least one control winding wound on said core for magnetizing of saidcore with said gate legs being similarly magnetized in the samedirection as the magnetization established by current in thecorresponding gate winding, and

a feedback circuit connected to said load circuit means and to saidcontrol winding and energizing said control winding in accordance withthe polarity and level of a control voltage and of the output voltage toestablish an output amplitude in direct proportion to the input signal.

2. The control unit of claim 1 wherein the middle arm and one end armdefining said gate legs having one-half the cross section area of theopposite end arm to saturate prior to the opposite end arm.

3. A magnetic control unit, comprising a multiple apertured magneticcore defining a magnetic control path, a part of which comprises a pairof adjacent parallel gate legs and a magnetic saturating path includingthe gate legs and the immediately adjacent bridging portion of thecontrol path, said core having an essentially square hysteresis loopcharacteristic and said legs being adapted to be saturated while theremainder of said control path is essentially below saturation,

at least one pair of gate windings provided, one winding on each of saidgate legs,

a load circuit means connecting said gate windings in circuit toalternating current input means having a varying current amplitudewithin each half cycle of the current input, an output connection meansand including selection means connecting said gate windings to conductthe alternate half cycle of the alternating current input, said gatewindings being constructed and connected to establish oppositelydirected flux loop including said gate leg and the immediately adjacentportion of the core bridging said two gate legs to define a saturatingmagnetic amplifier means,

at least one control winding wound on said core for magnetizing of saidcore with said gate legs being similarly magnetized in the samedirection as the magnetization established by current in thecorresponding gate winding, and

a feedback circuit connected to said load circuit means and to saidcontrol winding and energizing said control winding in accordance withthe polarity and level of a control voltage and of the output voltage toestablish an output amplitude in direct proportion to the input signal,

said gate windings are connected in circuit branches which areparalleled with each other and in series with alternating current inputmeans and the output connection means, said selection means includingunidirectional conductive means series connected one each in each ofsaid circuit branches, load connection means connected in series with atriggered switch means across the paralleled connection of saidbranches, a trigger signal means connected across the output connectionmeans, and means connecting the triggered switch means to the signalmeans to trigger said switch during each half cycle in accordance withthe level of magnetization of said control path.

4. The control unit of claim 3- wherein said triggered switch means is abilateral semiconductor switch means a 1 1 having a gate element, saidsignal means being impedance means connected to the gate element totrigger the switch means in response to the alternating currentestablished by saturation of said gate legs.

5. The control unit of claim 3 wherein said triggered switch meansinclude a pair of paralleled unidirectional semiconductor controlledrectifier means each having a gate element, and a coupling transformerhaving a primary winding connected across the output connection meansand a pair of secondary windings connected one each to the gate elementsto trigger the switch means in response to the alternating currentestablished by saturation of said gate legs.

6. A magnetic control unit, comprising a multiple apertured magneticcore defining a magnetic control path, a part of which comprises a pairof adjacent parallel gate legs and a magnetic saturating path includingthe gate legs and the immediately adjacent bridging portion of thecontrol path, said core having an essentially square hysteresis loopcharacteristic and said gate legs being adapted to be saturated whilethe remainder of said control path is essentially below saturation,

at least one pair of gate windings provided, one winding on each of saidgate legs,

a line frequency power input means connecting said gate windings incircuit to alternating current power of essentially sixty cycles persecond and essentially a sine wave, and including output connectionmeans having selection means connecting said gate windings to conductthe alternate half cycle of the alternating current input, said outputconnection means including a gated switch means having an input meansconnected to the gate "windings for selectively turning on said gatedswitch means in accordance with the conduction through said windings,said gate windings establishing oppositely directed flux loops includingsaid gate legs and the immediately adjacent portion of the core bridgingsaid two gate legs to define a saturating magnetic amplifier means,

at least one control winding wound on said core for magnetizing of saidcore with said gate legsbeing similarly magnetized in the same directionas the magnetization established by current in the corresponding gatewinding and the level of magnetization being selectively set to controlthe period of each half cycle of the sine wave conducted by said gatewindings and thereby the time of turning on of the gated switch means,and

a feedback circuit connected to said load circuit means and to saidcontrol winding and energizing said control winding in accordance withthe polarity and level of a control voltage and of the output voltage toestablish an output amplitude in direct proportion to the input signal.

7. The magnetic control unit of claim 6 wherein said gated switch meansis a controlled rectifier having an input gate means connected to saidgate windings.

References Cited UNITED STATES PATENTS TERRELL W. FEARS, PrimaryExaminer GARY M. HOFFMAN, Assistant Examiner US. Cl. X.R. 307-88 PatentNo.

Dated July 2].,

InventorOI) Column 9,

Claim 1 Column 10,

Claim 3 Column 10,

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CHARLES F. STRAWN It is certified that error appears in theabove-identified patent and that said Letters Patent are herebycorrected as shown below:

cancel "It" and substitute cancel "and" and substitute ---said---;

after "said" insert --gate--.

SIGNED ANu QEALEP WILLIAM R- sown-m. Jae Gomissioner of ram FORM PO-105O(10-69) USCOMM-DC 5O376-F'59 U.S. GOVERNMENT PRINTING OFFICE: Ill,0-35.!!!

